SONOS (Silicon Oxide Nitride Oxide Silicon) memories use single ended current sensing to reduce chip area. SONOS bi-gate memory cells include a pass transistor and a SONOS cell. The read current of the memory cell is modulated by VCC significantly (up to, for example, 8 uA/V) due to the pass transistor's VCC dependence. This causes read failures due to significant degradation of sense margin. A conventional solution uses a double ended to sensing scheme to track VCC dependence. Since there is no reference current involved and the current modulation due to pass transistors is a common mode signal for the bitline and the bitline-bar side, the VCC modulation effect on the final read speed and sense margin is removed. Unfortunately, these sort of differential read schemes involve two cells per bit of storage leading to poor area efficiency.
Another conventional solution uses a single ended sensing scheme with a pair of dummy column memory cells (one column for program cells and one column for erase cells) for every block of the array to obtain a reference current. The currents from the dummy columns of memory cells when added together can be mirrored to supply a reference cell current that is the center of program and erase current. Since the VCC modulation due to the pass transistor is common mode for the dummy columns of memory cells and the cell being accessed, the final read speed and sense margin were unaffected by pass transistor VCC modulation. Unfortunately, single ended sensing schemes that use a pair of dummy column cells to generate a reference current are less efficient in terms of chip area than a single ended sensing scheme that does not use dummy column of cells
Non-volatile memories that use single ended sensing schemes need a current sensing scheme that automatically tracks the VCC modulation of the memory cell to achieve better sense margin and high speed sensing.